1. Field of the Invention
The present invention relates to a semiconductor memory device, and in particular to a dynamic random access memory (DRAM) formed on an SOI (Silicon On Insulator) substrate.
2. Description of the Background Art
In general, semiconductor memory devices are broadly classified into volatile memories such as an RAM and non-volatile memories such as an ROM. The non-volatile memories are broadly classified into DRAMs and static random access memories (SRAMs). Non-volatile memories are broadly classified into a mask ROM, an EPROM, a flash memory, an EEPROM and a fuse ROM. Since the DRAM stores data by accumulating electric charges in a cell capacitor, it requires a refresh operation. However, memory cells have a simple structure. Therefore, DRAMs having a large-scale memory capacity can be formed with a low cost.
The memory cell of DRAM is generally formed of a transfer gate formed of an N-channel MOS transistor and a cell capacitor. The transfer gate is connected between a bit line and a cell capacitor, and has a gate electrode connected to a word line. When the potential of word line rises, the transfer gate is turned on. Thereby, electric charges accumulated in the cell capacitor flow onto the bit line via the transfer gate in the read operation, and the electric charges on the bit line flow into cell capacitor via the transfer gate in the write operation. Therefore, the memory cell holds binary data of "0" (logical low) or "1" (logical high) in accordance with the state of potential in cell capacitor.
Since the DRAM is generally formed on a silicon substrate, .alpha.-particles emitted from a material of interconnection or the like are injected into the silicon substrate, so that data stored in the cell capacitor may be inverted. Thus, a so-called soft error may occur.
Meanwhile, further increase of the degree of integration of DRAMs has been desired, and it is now expected that DRAMs having a large-scale storage capacity such as 256 Mbits or 1 Gbit will be mass-produced in a near future. In order to improve the degree of integration of DRAM, it is generally necessary to reduce the gate length. However, reduction of the gate length remarkably causes a short channel effect, so that the gate length can be reduced only to a limited extent.
In view of the foregoing, a DRAM may be formed on an SOI substrate including an insulating layer buried in a semiconductor substrate.
In the DRAM formed on the SOI substrate, a body region of a transfer gate forming a memory cell is electrically floated. Here, the body region is a region located between a source region and a drain region of the transfer gate. The body region corresponds to a bulk silicon substrate itself in a conventional DRAM formed on the bulk silicon substrate.
FIG. 67 shows capacity coupling with respect to the body register in a memory cell and its peripheral portion. Referring to FIG. 67, a node 1 of a word line is coupled to a node 4 of a body region via a gate capacity Cg. A node 2 of a bit line is coupled to node 4 of the body region via a parasitic capacity Cd which is necessarily formed at a PN junction region. A node 3 of a cell plate is coupled to body region 4 via a cell capacity Cs. Cell capacity Cs also includes parasitic capacities between the body region and source/drain regions of the transfer gate. The semiconductor substrate is connected to the body region via an insulating layer buried in the semiconductor substrate, so that a capacity Cbg is formed between the semiconductor substrate and the body region in accordance with a potential Vsub of the semiconductor substrate. Therefore, the semiconductor substrate is coupled to body region 4 via capacity Cbg. In FIG. 67, Vwl indicates the potential of word line. Vbit indicates the potential of bit line. Vcp indicates the potential of cell plate.
As described above, the body region is electrically floated and is coupled to the bit line via parasitic capacity Cd. In the unselected memory cells, therefore, such a problem may arise that electric charges of cell capacitors leak through the transfer gates. More specifically, in the read or write operation, potential Vbit of bit line rises from an intermediate potential of (Vccs-Vss)/2, which will be expressed as "Vccs/2" hereafter, to a power supply potential Vcc. Such variation of the potential of bit line is transmitted to the body region via parasitic capacity Cd, so that a potential Vbody of the body region rises only .DELTA.V as shown at (b) in FIG. 68. The SOI device is generally designed and manufactured such that capacity Cbg may be small in order to suppress the influence by the substrate potential. If the capacity Cbg is significantly smaller than any one of capacities Cg, Cd and Cs, .DELTA.V can be expressed by the following formula. EQU .DELTA.V=(1/2)Vcc.multidot.Cd/(Cd+Cg+Cs)
If potential Vbody of the body region of transfer gate rises as described above, the substrate effect reduces its threshold voltage, which promotes flow of the subthreshold current. Therefore, leak through the transfer gate tends to change the potential state of cell capacitor. This results in a high possibility of breakage of data.